1. Field of the Invention
The present invention relates to an apparatus for and method of manufacturing a semiconductor package, and more particularly, to an apparatus for and method of constructing a semiconductor package by performing a wire bonding process with respect to a wide lead frame.
2. Description of the Related Art
As use of mobile phones and laptops has constantly increased, such electronic apparatuses have been developed to be more compact, lighter, and have more functions. Accordingly, electronic parts used for use in these electronic apparatuses need to be made smaller and with higher integration density. To meet the needs, along with a method of highly integrating a semiconductor chip to decrease its size, a method of mounting a semiconductor chip using a multi-chip packaging technology has been widely used.
FIG. 1 is a cross-sectional view illustrating the structure of a conventional dual die package (DDP). Referring to FIG. 1, two semiconductor chips, that is, first and second semiconductor chips 11 and 13, are mounted on a lead frame 20. The lead frame 20 includes a die pad 21 and a lead finger 23. The first and second semiconductor chips 11 and 13 are respectively attached to the upper and lower surfaces of the die pad 21 via first and second adhesive layers 25 and 26. The first and second semiconductor chips 11 and 13 are electrically connected to the lead finger 23 via wire bonds 27 and 28. The first and second semiconductor chips 11 and 13, the wire bonds 27 and 28, and their junction portions are sealed by a molding resin 15 such as epoxy molding compound so as to be protected from an external environment.
FIG. 2 is a cross-sectional view illustrating the structure of a conventional quad die package (QDP). Referring to FIG. 2, four semiconductor chips are mounted on a lead frame 40 including a die pad 41 and a lead finger 43. That is, first and second semiconductor chips 31 and 33 are sequentially deposited on the upper surface of the die pad 41 by being attached to first and second adhesive layers 45 and 47. Third and fourth semiconductor chips 35 and 37 are sequentially deposited on the lower surface of the die pad 41 by being attached to third and fourth adhesive layers 46 and 48. The first through fourth semiconductor chips 31, 33, 35, and 37 are electrically connected to the lead finger 43 via wire bonds 51, 53, 55, and 57. The first through fourth semiconductor chips 31, 33, 35, and 37, the wire bonds 51, 53, 55, and 57, and their junction portions are sealed by a molding resin 61 such as epoxy molding resin.
The process of manufacturing a single semiconductor chip package and a semiconductor package using a lead frame in the DDP and QDP structures shown in FIGS. 1 and 2, includes a wire bonding process for separating a unit semiconductor chip from a wafer where integrated circuits (ICs) are formed and attaching the separated unit semiconductor chip to a lead frame, a wire bonding process for bonding the semiconductor chip and the lead frame using a conductive metal wire so as to be electrically connected therebetween, a molding process for molding the electrically connected parts with molding resin to protect them from an external environment, a trim/form process for cutting and bending the lead finger that protrudes outside, and a test process for testing reliability of a complete IC chip package.
In the conventional semiconductor package manufacturing process, the lead frame is used for providing a place for mounting a semiconductor chip and as a means for an electrical connection. In this regard, as the competition in the market and development of semiconductor device technology has increased, productivity and cost reduction become more important issues. Conventionally, the lead frame is manufactured in a strip shape so that eight to ten semiconductor packages can be simultaneously manufactured. However, in order to increase the number of the semiconductor packages to be manufactured using a single lead frame, a wide lead frame having a wide width has been developed so that a number of semiconductor packages can be manufactured not only in the lengthwise direction of the lead frame but also in the widthwise direction of the lead frame.
However, in order to use the wide lead frame, a semiconductor package manufacturing equipment is necessary and the costs for developing and manufacturing such the equipment is high. Furthermore, the semiconductor chip package manufacturing process for multi-chip packaging requires a manual work so that a process time increases due to a process delay, and accordingly productivity, deteriorates.